Execution of condition-based instructions

ABSTRACT

Execution of condition-based instructions is facilitated. A condition-based instruction is obtained, as well as a confidence level associated with the instruction. The confidence level is checked, and based on the confidence level being a first value, a predicted operation of the instruction, which is based on a predictor, is unconditionally performed. Further, based on the confidence level being a second value, a specified operation of the instruction, which is based on a determined condition, is conditionally performed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending U.S. patent applicationSer. No. 13/832,542, filed Mar. 15, 2013, entitled “EXECUTION OFCONDITION-BASED INSTRUCTIONS,” which is hereby incorporated herein byreference in its entirety.

BACKGROUND

One or more aspects relate, in general, to processing within a computingenvironment, and in particular, to execution of condition-basedinstructions within such an environment.

Many types of instructions are used in a computing environment in orderto perform certain tasks and to control the environment. One type ofinstruction is a condition-based instruction, in which performance ofthe instruction depends on a particular condition. This condition may beset by yet another instruction. For instance, with a Load on Conditioninstruction, provided in the z/Architecture offered by InternationalBusiness Machines Corporation, a load is performed based on a conditioncode having one value (which is set by another instruction), and no loadis performed based on the condition code having another value.

Further, in other condition-based instructions, one datum is selectedbased on one value of a condition, and another datum is selected basedon another value of the condition.

BRIEF SUMMARY

Shortcomings of the prior art are overcome and advantages are providedthrough the provision of a method of facilitating execution of aninstruction in a computing environment. The method includes, forinstance, checking a confidence level associated with the instruction;based on the confidence level being a first value, unconditionallyperforming a predicted operation of the instruction, the predictedoperation based on a predictor associated with the instruction; andbased on the confidence level being a second value, conditionallyperforming a specified operation of the instruction, the specifiedoperation based on a determined condition.

Computer program products and systems relating to one or more aspectsare also described and may be claimed herein. Further, services relatingto one or more aspects are also described and may be claimed herein.

Additional features and advantages are realized through the techniquesof one or more aspects. Other embodiments and aspects are described indetail herein and are considered a part of the claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

One or more aspects are particularly pointed out and distinctly claimedas examples in the claims at the conclusion of the specification. Theforegoing and other objects, features, and advantages are apparent fromthe following detailed description taken in conjunction with theaccompanying drawings in which:

FIG. 1A depicts one example of a computing environment to incorporateand use one or more aspects;

FIG. 1B depicts further details of the processor of FIG. 1A;

FIG. 2A depicts another example of a computing environment toincorporate and use one or more aspects;

FIG. 2B depicts further details of the memory of FIG. 2A;

FIG. 3 depicts one embodiment of the logic to execute an instructionbased on a confidence level of a predictor;

FIG. 4A depicts one embodiment of a Load On Condition instruction;

FIG. 4B depicts another embodiment of a Load On Condition instruction;

FIG. 4C depicts one example of an Integer Select instruction;

FIG. 5 depicts one embodiment of the logic to execute a Load OnCondition instruction based on a confidence level of a predictor;

FIG. 6 depicts one embodiment of the logic associated with recovering acondition-based instruction;

FIG. 7 depicts one example of a pipe diagram for a Load On Conditioninstruction executed in accordance with the prior art;

FIGS. 8A-8H depict examples of various pipe diagrams for execution ofcondition-based instructions in accordance with one or more aspects;

FIG. 9 depicts one embodiment of a computer program productincorporating one or more aspects;

FIG. 10 depicts one embodiment of a host computer system;

FIG. 11 depicts a further example of a computer system;

FIG. 12 depicts another example of a computer system comprising acomputer network;

FIG. 13 depicts one embodiment of various elements of a computer system;

FIG. 14A depicts one embodiment of the execution unit of the computersystem of FIG. 13;

FIG. 14B depicts one embodiment of the branch unit of the computersystem of FIG. 13;

FIG. 14C depicts one embodiment of the load/store unit of the computersystem of FIG. 13; and

FIG. 15 depicts one embodiment of an emulated host computer system.

DETAILED DESCRIPTION

In accordance with one or more aspects, a capability is provided tofacilitate execution of machine instructions in a computing environment.In particular, a capability is provided to facilitate execution ofcondition-based instructions, in which execution may proceed withoutwaiting for a determination of the condition (e.g., an indication of theparticular operation) to be performed. To facilitate execution, in oneexample, a confidence level associated with the instruction is checked.The confidence level is part of a predictor or it is itself a predictor.Based on the confidence level, either execution proceeds as isconventional for that instruction or execution proceeds based on aprediction of the condition.

Examples of condition-based instructions are load conditionalinstructions, such as the Load On Condition (a.k.a., Move On Condition)instructions, offered by International Business Machines Corporation.Other examples of condition-based instructions are data selectioninstructions that select one datum or another based on a selectcondition, such as the Integer Select instruction of the PowerArchitecture offered by International Business Machines Corporation. Asused herein, datum refers to a data value and/or an operand, asexamples.

One embodiment of a computing environment to incorporate and use one ormore aspects is described with reference to FIG. 1A. A computingenvironment 100 includes, for instance, a processor 102 (e.g., a centralprocessing unit), a memory 104 (e.g., main memory), and one or moreinput/output (I/O) devices and/or interfaces 106 coupled to one anothervia, for example, one or more buses 108 and/or other connections.

In one example, processor 102 is based on the z/Architecture offered byInternational Business Machines Corporation, and is part of a server,such as the System z server, which implements the z/Architecture and isalso offered by International Business Machines Corporation. Oneembodiment of the z/Architecture is described in an IBM® publicationentitled, “z/Architecture Principles of Operation,” IBM® Publication No.SA22-7832-09, Tenth Edition, September, 2012, which is herebyincorporated herein by reference in its entirety. In one example, theprocessor executes an operating system, such as z/OS, also offered byInternational Business Machines Corporation. IBM®, Z/ARCHITECTURE® andZ/OS® are registered trademarks of International Business MachinesCorporation, Armonk, N.Y., USA. Other names used herein may beregistered trademarks, trademarks, or product names of InternationalBusiness Machines Corporation or other companies.

In a further embodiment, processor 102 is based on the PowerArchitecture offered by International Business Machines Corporation. Oneembodiment of the Power Architecture is described in “Power ISA™ Version2.06 Revision B,” International Business Machines Corporation, Jul. 23,2010, which is hereby incorporated herein by reference in its entirety.POWER ARCHITECTURE® is a registered trademark of International BusinessMachines Corporation.

In yet a further embodiment, processor 102 is based on an Intelarchitecture offered by Intel Corporation. One embodiment of the Intelarchitecture is described in “Intel® 64 and IA-32 ArchitecturesDeveloper's Manual: Vol. 2B, Instructions Set Reference, A-L,” OrderNumber 253666-045US, January 2013, and “Intel® 64 and IA-32Architectures Developer's Manual: Vol. 2B, Instructions Set Reference,M-Z,” Order Number 253667-045US, January 2013, each of which is herebyincorporated herein by reference in its entirety. Intel® is a registeredtrademark of Intel Corporation, Santa Clara, Calif.

Processor 102 includes a plurality of functional components used toexecute instructions. As depicted in FIG. 1B, these functionalcomponents include, for instance, an instruction fetch component 120 tofetch instructions to be executed; an instruction decode unit 122 todecode the fetched instructions and to obtain operands of the decodedinstructions; an instruction execute component 124 to execute thedecoded instructions; a memory access component 126 to access memory forinstruction execution, if necessary; and a write back component 130 toprovide the results of the executed instructions. One or more of thesecomponents may, in accordance with an aspect, provide predictivefunctionality by including at least a portion of or having access to aprediction component 136. This functionality is described in furtherdetail below.

Processor 102 also includes one or more registers, such as a register140 to hold a predictor data structure (e.g., table) that includes oneor more predictors. The predictor data structure is used by theprocessor, and in particular, the prediction component, as describedfurther below.

In a further embodiment, the predictor data structure is stored inmemory and accessed by processor 102. Yet further, a portion of thepredictor data structure may be maintained in one or more CPU registers,and a further portion is stored in memory or one or more externalstorage devices. Other embodiments are also possible.

Another register used by processor 102, in accordance with one or moreaspects, is a register 142 to include a mispredicted recovery indicator.In a further example, this indicator is stored in memory and accessed bythe processor. Other examples are also possible.

Another embodiment of a computing environment to incorporate and use oneor more aspects is described with reference to FIG. 2A. In this example,a computing environment 200 includes, for instance, a native centralprocessing unit 202, a memory 204, and one or more input/output devicesand/or interfaces 206 coupled to one another via, for example, one ormore buses 208 and/or other connections. As examples, computingenvironment 200 may include a PowerPC processor, a pSeries server or anxSeries server offered by International Business Machines Corporation,Armonk, New York; an HP Superdome with Intel Itanium II processorsoffered by Hewlett Packard Co., Palo Alto, Calif.; and/or other machinesbased on architectures offered by International Business MachinesCorporation, Hewlett Packard, Intel, Oracle, or others.

Native central processing unit 202 includes one or more native registers210, such as one or more general purpose registers and/or one or morespecial purpose registers used during processing within the environment.These registers include information that represents the state of theenvironment at any particular point in time.

Moreover, native central processing unit 202 executes instructions andcode that are stored in memory 204. In one particular example, thecentral processing unit executes emulator code 212 stored in memory 204.This code enables the processing environment configured in onearchitecture to emulate another architecture. For instance, emulatorcode 212 allows machines based on architectures other than thez/Architecture, such as PowerPC processors, pSeries servers, xSeriesservers, HP Superdome servers or others, to emulate the z/Architectureand to execute software and instructions developed based on thez/Architecture.

Further details relating to emulator code 212 are described withreference to FIG. 2B. Guest instructions 250 stored in memory 204comprise software instructions (e.g., correlating to machineinstructions) that were developed to be executed in an architectureother than that of native CPU 202. For example, guest instructions 250may have been designed to execute on a z/Architecture processor 102, butinstead, are being emulated on native CPU 202, which may be, forexample, an Intel Itanium II processor. In one example, emulator code212 includes an instruction fetching routine 252 to obtain one or moreguest instructions 250 from memory 204, and to optionally provide localbuffering for the instructions obtained. It also includes an instructiontranslation routine 254 to determine the type of guest instruction thathas been obtained and to translate the guest instruction into one ormore corresponding native instructions 256. This translation includes,for instance, identifying the function to be performed by the guestinstruction and choosing the native instruction(s) to perform thatfunction.

Further, emulator 212 includes an emulation control routine 260 to causethe native instructions to be executed. Emulation control routine 260may cause native CPU 202 to execute a routine of native instructionsthat emulate one or more previously obtained guest instructions and, atthe conclusion of such execution, return control to the instructionfetch routine to emulate the obtaining of the next guest instruction ora group of guest instructions. Execution of the native instructions 256may include loading data into a register from memory 204; storing databack to memory from a register; or performing some type of arithmetic orlogic operation, as determined by the translation routine.

Each routine is, for instance, implemented in software, which is storedin memory and executed by native central processing unit 202. In otherexamples, one or more of the routines or operations are implemented infirmware, hardware, software or some combination thereof. The registersof the emulated processor may be emulated using registers 210 of thenative CPU or by using locations in memory 204. In embodiments, guestinstructions 250, native instructions 256 and emulator code 212 mayreside in the same memory or may be disbursed among different memorydevices.

As used herein, firmware includes, e.g., the microcode, millicode and/ormacrocode of the processor. It includes, for instance, thehardware-level instructions and/or data structures used inimplementation of higher level machine code. In one embodiment, itincludes, for instance, proprietary code that is typically delivered asmicrocode that includes trusted software or microcode specific to theunderlying hardware and controls operating system access to the systemhardware.

In one example, a guest instruction 250 that is obtained, translated andexecuted is an instruction described herein. The instruction, which isof one architecture (e.g., the z/Architecture) is fetched from memory,translated and represented as a sequence of native instructions 256 ofanother architecture (e.g., PowerPC, pSeries, xSeries, Intel, etc.).These native instructions are then executed.

In accordance with one aspect, processing of certain types ofinstructions, such as condition-based instructions, is facilitated byuse of a predictor that enables selection of one execution path overanother execution path. The predictor depends on the instruction, andhas, for instance, a confidence level and a prediction. The confidencelevel includes an indication of strong (or high) or weak (or low); andthe prediction is one of a plurality of operations, depending on theinstruction. For instance, for a load conditional instruction, theprediction is either to perform a load operation (load) or suppress aload operation (no load); and for a data selection instruction, theprediction is either a selection of a first datum (select A) or aselection of a second datum (select B), as examples. In a furtherexample, there are multiple predictors: one to provide the confidenceand one to provide the predicted operation. Other examples are alsopossible.

One embodiment of the logic to execute an instruction based on apredictor associated with the instruction is described with reference toFIG. 3. In one example, this logic is performed by a processor.

Referring to FIG. 3, initially, based on receiving an instruction to beexecuted, a predictor corresponding to that instruction is checked, STEP300. In particular, in one embodiment, for each instruction that is tobe executed based on prediction, there is a predictor associatedtherewith. The predictor is, for instance, a saturating counter orbimodal predictor, which is a state machine with four states encoded, asfollows: 11 (binary) Strongly Predicted A (e.g., load, select datum A);01 Weakly Predicted A (e.g., load, select datum A); 00 Weakly PredictedB (e.g., no load, select datum B); and 10 Strongly Predicted B (e.g., noload, select datum B). The leftmost bit indicates the confidence; i.e.,strong or weak; and the rightmost bit indicates the decision oroperation; e.g., no load, load, select A, select B. Again, in a furtherexample, there are two predictors: one for the confidence level, and onefor the predicted operation. The current predictor for an instruction ismaintained in a table or other data structure, which is indexed by theinstruction address bits, and stored, for instance, in a register (e.g.,register 140), memory, etc.

Based on obtaining the instruction, the predictor is obtained for thatinstruction, and the confidence level of the predictor is checked todetermine the confidence of correctly predicting the condition (e.g.,the operation to be performed). If the confidence level is high, INQUIRY302, then a predicted operation, which is indicated by the predictor, isunconditionally performed. For instance, if the predictor has a value of11, and the instruction is the load instruction, then the load isunconditionally performed. Similarly, if the predictor has a value of11, and the instruction is a data selection instruction, then datum A isselected. This unconditional processing is further described below.

Continuing with INQUIRY 302, should it be determined that the confidencelevel for the predictor is high, then, in one embodiment, an executionimplementation is generated to unconditionally perform the conditionbased on the prediction, STEP 304. In one embodiment, theunconditionally performing occurs speculatively. The implementationincludes, for instance, generating one or more internal operations(IOPs), but in other embodiments, it includes using microcode or a statemachine, etc. Thus, in one example of the load instruction, internaloperations are generated to perform the load.

In addition to the above, an indication is generated to check theprediction, STEP 306. This indication is to check whether the predictionwas accurate, and again, as examples, it is implemented via internaloperations, a state machine, microcode, or other types ofimplementations.

For instance, as a particular example, assume a load conditionalinstruction, LC Rn=Rx, is to be unconditionally executed. To accomplishthis, the decode process generates a sequence of one or more internalinstructions unconditionally corresponding to the action that ispredicted, as well as a check operation. Thus, for LC Rn=Rx, in oneembodiment, a load register internal instruction (LR IOP), such as LRRn=Rx, is generated and executed, as well as a check internalinstruction (e.g., check IOP).

Thereafter, the operation (e.g., LR IOP) is unconditionally performed,STEP 308. This includes, in one example, executing the unconditionalinternal operations previously generated. Thus, in one example, the loadis unconditionally performed, since the predictor had a value of 11, inthis particular example. Additionally, the prediction data structure isupdated, based on the prediction, STEP 310.

Subsequently, the prediction is checked (e.g., check IOP), STEP 312. Inparticular, for a Load on Condition instruction, when the inputcondition code actually becomes available which indicates what operationis to be performed (e.g., load, no load), a determination is made as towhether the prediction was correct. If the prediction was not correct,INQUIRY 314, then recovery code is executed, STEP 316. However, if theprediction was correct, then execution of the instruction is completed,STEP 318.

Returning to INQUIRY 302, if the confidence level is low, then animplementation is provided to conditionally perform the operation basedon a determination of the actual condition, STEP 320. Thisimplementation includes, in one example, generating internal operations;however, in further examples, it includes implementing the operation inmicrocode or with state machines, as examples. Thus, in this executionalpath, the instruction waits for an indication of the actual operation tobe performed (e.g., a condition code to be set or a register to beupdated to indicate the operation). For instance, for a Load onCondition instruction that performs the operation based on a conditioncode, the instruction actually waits for the condition code, which isset by another instruction.

Subsequently, the conditional internal operations that were generatedare executed, STEP 322, and the prediction data structure is updatedbased on the execution, STEP 324. Processing then continues to STEP 318,in which the instruction is completed.

As indicated above, one example of an instruction to use the logic ofFIG. 3 is a Load On Condition instruction, which is also referred to asa Move On Condition instruction. Examples of Load On Conditioninstructions are depicted in FIGS. 4A and 4B, and described below.

Referring to FIG. 4A, a Load On Condition instruction 400 is described.In this example, the format of the instruction is aregister-and-register format (e.g., LOCR-operands are 32 bits;LOCGR-operands are 64 bits), and it includes: an opcode field 402 (e.g.,bits 0-15) to include an opcode to indicate a load on conditionoperation; a mask field (M₃) 404 (e.g., bits 16-19) to provide a mask ofcondition codes; a first register field 406 (e.g., bits 24-27) used todesignate a first register (R₁); and a second register field 408 (e.g.,bits 28-31) used to designate a second register (R₂). Each of the fields404-408, in one example, is separate and independent from the opcodefield. Further, in one embodiment, they are separate and independentfrom one another; however, in other embodiments, more than one field maybe combined.

In one example, selected bits (e.g., the first two bits) of the opcodedesignated by opcode field 402 specify the length of the instruction. Inthis particular example, the selected bits indicate that the length istwo halfwords. Further, with this instruction format, the contents ofthe register designated by the R₁ field are called the first operand,and the contents of the register designated by the R₂ field are calledthe second operand.

A further embodiment of a Load On Condition instruction 450 is describedwith reference to FIG. 4B. In this example, the format of theinstruction is a register-and-storage format (e.g., LOC-operands are 32bits; LOCG-operands are 64 bits), and it includes: opcode fields 452 a(e.g., bits 0-7), 452 b (e.g., bits 40-47) to include an opcode toindicate a load on condition operation; a first register field 454(e.g., bits 8-11) used to designate a first register (R₁); a mask field456 (e.g., bits 12-15) used to designate a mask (M₃), and a base field(B₂) 458 (e.g., bits 16-19), a first displacement field (DL₂) 460 (e.g.,bits 20-31), and a second displacement field (DH₂) 462 (e.g., bits32-39) used to form the second operand address. In particular, thecontents of the general register designated by the B₂ field are added tothe contents of the DH₂ and DL₂ fields to form the second operandaddress. In one example, the displacement (DH₂ and DL₂) for LOC and LOCGis treated as a 20-bit signed binary integer.

In one example, selected bits (e.g., the first two bits) of the opcodedesignated by opcode field 452 a specify the length of the instruction.In this particular example, the selected bits indicate that the lengthis three halfwords. Further, with this instruction format, the contentsof the register designated by the R₁ field are called the first operand.

In execution of one embodiment of the Load On Condition instruction,regardless of format, the second operand is placed unchanged at thefirst operand location if the condition code is one of the valuesspecified by the M₃ field and that value is set to one. Otherwise, thefirst operand remains unchanged.

For example, the M₃ field is used as a four bit mask. The four conditioncodes (0, 1, 2 and 3) correspond, left to right, with the four bits ofthe mask, as follows:

Condition Code Mask Position Value 0 8 1 4 2 2 3 1

The current condition code is used to select the corresponding mask bit.If the mask bit selected by the condition code is 1, the load isperformed. If the mask bit selected is 0, the load is not performed.

For LOC and LOCG, when the condition specified by the M₃ field is notmet (that is, the load operation is not performed), it is modeldependent whether an access exception or a PER (Program EventRecording)-zero address detection event is recognized for the secondoperand.

One example of another instruction to use the prediction capability ofFIG. 3 is an Integer Select (isel) instruction based on the PowerArchitecture, offered by International Business Machines Corporation. Asshown in FIG. 4C, an Integer Select instruction 470 includes, forinstance: opcode fields 472 a, 472 b to indicate an opcode to specifythe integer select operation; a first register field (RT) 474 todesignate a first register; a second register field (RA) 476 todesignate a second register; a third register field (RB) 478 todesignate a third register; and a datum field (BC) 480 to include avalue to be used by the instruction.

In execution of one embodiment of this instruction, if the contents ofbit BC+32 of a condition register (CR) are equal to one, then thecontents of register RA (or 0) are placed into register RT. Otherwise,the contents of register RB are placed into register RT.

Further details relating to using a predictor with the Load On Conditioninstructions and the data selection instructions are described below.Initially, Load on Condition is described, and then, data selection. Inone example, the logic is performed by a processor.

One embodiment of the logic to use prediction with a Load On Conditioninstruction is described with reference to FIG. 5. Initially, based onreceiving the Load On Condition instruction to be executed, thepredictor corresponding to the Load On Condition instruction is checked,STEP 500. If the confidence level is high, INQUIRY 502, then a predictedload conditional, which is indicated by the predictor, isunconditionally performed, STEP 504. For instance, if the predictor hasa value of 10 and the instruction is the Load On Condition instruction,then suppression of the load is unconditionally performed. That is, thefirst operand remains unchanged. As a further example, if the predictorhas a value of 11 and the instruction is the Load on Conditioninstruction, then the load is unconditionally performed.

Continuing with INQUIRY 502, should it be determined that the confidencelevel for the predictor is high, then, in one embodiment, an executionimplementation is generated to unconditionally perform the conditionbased on the prediction, STEP 504. In one example, the executionimplementation includes generating one or more internal operations(IOPs), but in other embodiments, it includes using microcode or a statemachine, etc. Thus, in one example of the load instruction, internaloperations are generated to suppress the load or perform the load,depending on the predictor.

In addition to the above, an indication is generated to check theprediction, STEP 506. This indication is to check whether the predictionwas accurate, and again, as examples, it is implemented via internaloperations, a state machine, microcode, or other types ofimplementations.

Thereafter, the operation is unconditionally performed, STEP 508. Thisincludes, in one example, executing the unconditional internaloperations previously generated. Thus, in one example, suppression ofthe load is unconditionally performed, since the predictor had a valueof 10, in this particular example. Additionally, the prediction datastructure is updated, STEP 510.

Subsequently, the prediction is checked, STEP 512. In particular, for aLoad on Condition instruction, when the condition code actually becomesavailable, which indicates what operation is to be performed (e.g.,load, no load), a determination is made as to whether the prediction wascorrect. If the prediction was not correct, INQUIRY 514, then recoverycode is executed, STEP 516. However, if the prediction was correct, thenexecution of the instruction is completed, STEP 518.

Returning to INQUIRY 502, if the confidence level is low, then animplementation is provided to conditionally perform the operation basedon a determination of the actual condition, STEP 520. Thus, in thisexecutional path, the instruction waits for an indication of the actualoperation to be performed. For instance, for a Load on Conditioninstruction, the instruction actually waits for the condition code,which is set by another instruction and provided as an input to the Loadon Condition instruction. To perform the conditional execution, anexecution implementation is generated, which in one example, includesgenerating internal operations; however, in further examples, itincludes implementing the operation in microcode or with state machines,as examples.

Subsequently, the conditional internal operations that were generatedare executed, STEP 522, and the prediction data structure is updatedbased on the execution, STEP 524. Processing then continues to STEP 518,in which the instruction is completed.

Although the above logic is described with reference to a Load OnCondition instruction, it is also applicable to other condition-basedinstructions, such as data selection instructions. In one instance, fora data selection instruction, the “load-conditional” of FIG. 5 isreplaced with “select”.

One embodiment of the recovery performed should the prediction for acondition-based instruction (e.g., a Load On Condition or a dataselection instruction) be incorrect is described with reference to FIG.6. In one example, this logic is performed by a processor, and inparticular, fetch and decode components of a processor.

Referring to FIG. 6, initially, an instruction is fetched, STEP 600, anda determination is made as to whether misprediction recovery isindicated, INQUIRY 602. This may be indicated in a register (e.g.,register 142), memory or by any other mechanism. If recovery is notindicated, then a further determination is made as to whether theinstruction that was fetched is a condition-based instruction, INQUIRY604. If it is not a condition-based instruction, then conventionaldecoding of the instruction is performed, STEP 606, and processingcontinues with STEP 600. However, if it is a condition-basedinstruction, then a look-up is performed in the predictor table to findthe current predictor for this instruction, STEP 608. The confidencelevel of the predictor is checked. If it is a high confidence, INQUIRY610, then, in one example, an implementation (e.g., internal operations)is generated to unconditionally perform the predicted operation, STEP612. Further, an implementation (e.g., internal operations) to check theprediction is also generated, STEP 614.

Subsequently, the generated internal operations are placed on an issuequeue in order to be executed, STEP 616, and processing continues toSTEP 600.

Returning to INQUIRY 610, if the confidence level is low, animplementation (e.g., internal operations) is generated to conditionallyperform the operation, which is based on a determined condition, STEP618. The implementation is placed on the issue queue, STEP 620, andprocessing continues to STEP 600.

Returning to INQUIRY 602, if a misprediction recovery is indicated, thenflushing of the instruction pipeline is performed back to, for instance,the condition-based instruction, STEP 630. That is, in an instructionpipeline, there may be multiple instructions being processedconcurrently, each at a different stage of processing (e.g., instructionfetch (IF), instruction issue or decode, register file access (RF) usedto access values of registers to be used in execution, execute (EX), orresult write back (WB) used to provide results of the execution). Thus,after one instruction ends one stage, such as the instruction fetchstage, and begins another stage, such as the decode stage, anotherinstruction can begin the instruction fetch stage, etc. If there is amisprediction recovery, the pipeline is flushed back to thecondition-based instruction. That is, the instructions in the pipelinethat started after the condition-based instruction are backed-out inorder to restart a correct execution of the condition-based instruction.

Additionally, a condition-based misprediction recovery sequence isgenerated, STEP 632. For instance, internal operations are generated toperform recovery. This includes, for instance, re-fetching theinstruction and performing the opposite operation. For example, if aLoad On Condition instruction was executed and the operation performedwas a load, then the Load On Condition instruction is re-executed andthe load is suppressed. As a further example, if a data selectioninstruction was executed and the operation performed was Select A, thenthe instruction is re-executed and datum B is selected.

In a further embodiment, the instruction is re-executed, but noinformation is given on how it is to proceed in the re-execution. Itsimply re-executes as previously described, using, for instance, a lowconfidence execution path, i.e., based on accessing the condition toavoid further mis-executions based on misprediction of the condition. Atthis point the condition is available, having been used to checkcorrectness of the prediction (e.g., in accordance with a checking step,such as STEP 512 of FIG. 5).

The generated internal operations are then placed on the issue queue tobe executed, STEP 634, and processing continues to STEP 600.

The effects of prediction and misprediction are further understood withreference to the example pipe diagrams depicted in FIGS. 7-8H. In eachof these figures, the vertical lines depict example cycle boundaries andtime passes from left to right. FIG. 7 is one example of a pipe diagramin which prediction is not used. As depicted, a long-running conditioncode (cc) producing chain 700 is executing and at time 702 a conditioncode 704 is written. In the meantime, a load conditional instruction (LCRn=Rx) 706 is fetched 708 (IF—Instruction Fetch). However, processing ofthe instruction within the instruction pipeline is stalled 710 untilcondition code 704 is available. After the condition code is written,then the remaining stages of the instruction pipeline, including, forinstance, issue 714, register file access (RF) 716, execution (EX) 718,and write back (WB) 720 are executed.

Similarly, processing of instruction AR 730 is affected, since AR 730 isdependent on execution of LC 706 which provides the Rn to be used by AR730. Therefore, as shown, AR 730 is fetched 732; however, processing isstalled 734 waiting for Rn. After Rn is available, then processing of ARcontinues, including, for instance, issue 736, register file access 738,execution 740 and write back 742.

The pipe diagram of FIG. 7 is compared to the pipe diagrams of FIGS.8A-8H. Each of these diagrams, including FIG. 7, shows a number ofexample processing stages. In other examples, other stages may be usedor stages may be in a differing order. Many possibilities exist.

Referring initially to FIG. 8A, a pipe diagram is depicted showing ahigh confidence level that selected predictive mode with a correctprediction, in which a data load was predicted. In FIG. 8A, along-running cc producing chain 800 is processing, and at time 802, acondition code 804 is written. Further, a Load Conditional (LC Rn=Rx)instruction 806 is initiated. In this example, since prediction is used,the LC instruction is replaced (during decode, which may be a part offetch or issue, as examples) with a check TOP 808 and an unconditionalLR 820 to reflect the prediction that the load is to be performedunconditionally, but speculatively. Thus, a check internal operation808, which is to check if the prediction was accurate, is generated(e.g., using instruction fetch (IF) 810 and decode logic andcorresponding to, e.g., STEP 506 of FIG. 5). This instruction stalls 812depending on condition code 804. Further, a load register internaloperation (LR Rn=Rx) 820 is generated (e.g., using instruction fetch 822and decode logic and corresponding to, e.g., STEP 504). Since predictionis used, it need not stall, but instead, processing continues with, forinstance, instruction issue 824, register file access 826, execution828, and write back 830. Similarly, instruction 840 is fetched 842. Thisinstruction stalls 844 depending on the value of Rn; however, unlike inFIG. 7, Rn should be available much sooner. Processing then continueswith, for instance, issue 846, register file access 848, execute 850 andwrite back 852. Additionally, optimization is performed and one or moreof stages 846-852 are initiated prior to receiving Rn.

Returning to stall 812, after the condition code is available,processing continues with, for instance, issue 814, register file access816, and execute in which a check 818 of the prediction is performed.

FIG. 8B depicts another example of a pipe diagram, but this diagramshows a high confidence that selects a predictive mode with correctprediction and no data load is predicted. Therefore, the value of Rn isreadily available for AR 840. Check IOP 808 still stalls 812 waiting forcondition code 804, since prediction was used.

In FIG. 8C, one example of a pipe diagram is depicted that has a lowconfidence, and therefore, it selects stall on data dependence as shownat 812. For instance, a load conditional (LC) internal operation 806 isgenerated (e.g., using instruction fetch and decode) and stalls 812waiting for condition code 804. Similarly AR 840 also stalls 844 waitingfor Rn.

FIG. 8D depicts one example in which there is recovery due to anincorrect prediction. In particular, FIG. 8D depicts one example of apipe diagram in which the high confidence selects predictive mode, inwhich data load is predicted, but the prediction is incorrect. In thisscenario, a check operation 862 that is performed during execution, whencondition code 804 is available, indicates a misprediction. Therefore,the check operation causes a recovery to be performed, including a flushand refetch 864. In the recovery, LC 806 is refetched 866 and processedusing the available condition (e.g., previously used by check). However,in this example, the load is suppressed 867, since the prediction ofload was incorrect. Further, AR 840 is also refetched 869 and processed(e.g., issue, register file access, execute, write back).

Similarly FIG. 8E depicts one example of a pipe diagram in which highconfidence selects predictive mode in which no data load is predicted,but the prediction is incorrect. In this scenario, a load is to beperformed, since the prediction of no load was incorrect. Thus, aninternal instruction 820 is generated (e.g., using instruction fetch 870and decode), and processed (e.g., issue, register file access, executeand write back). Further, instruction AR 840 stalls 872 depending on Rn.

FIG. 8F is one example of a pipe diagram for a data selectioninstruction in which there is high confidence that selects a predictivemode with a correct prediction of an S1 data load. This is similar toFIG. 8A, but instead of a condition code, there is a condition register880, and instead of a load conditional instruction, there is an integerselect instruction 882. The processing is similar, but instead of aload, a data selection of a first operand 884 is performed.

Similarly, FIG. 8G depicts one example of a pipe diagram in which thereis high confidence and predictive mode is selected with a correctprediction of an S2 data load. Thus, in this example, the second operand886 is selected.

FIG. 8H depicts one example of a pipe diagram for an ISEL instruction inwhich there is low confidence, and therefore, there is a stall 890 ondata dependents (e.g., control register 880).

Described in detail above is one example of using predictors tofacilitate execution of condition-based instructions. A predictor isobtained for a condition-based instruction to be executed, and aconfidence level of the predictor is checked. If the confidence level ishigh, then the condition-based instruction is executed based on theprediction and without waiting for the actual condition to bedetermined. This allows the condition-based instruction and instructionsthat are dependent on the condition-based instruction to be executedfaster than if waited for the condition to actually be determined. Ifthe confidence level of the predictor is low, then the condition-basedinstruction stalls waiting for the actual condition to be determined.

In one example, the predictor is obtained from a predictor table;however, in another embodiment, the predictor is encoded within theinstruction (e.g., one or more bits of the instruction). This enables aprogrammer or other to provide guidance as to whether prediction is tobe used. Further, in another embodiment, prior to proceeding with theprediction, a determination is made as to whether an up-to-datecondition code (or other condition) is available. If so, then the actualvalue of the condition is used rather than the predicted condition. Asexamples, the condition may be provided as a condition code or in aregister, such as a condition register, a general purpose register, afloating point register, etc. The condition is input to the instructionbeing executed based on the predictive functionality.

In one example, there are multiple predictors: a first predictor(confidence level) provides selection of one execution path of aplurality of execution paths for an instruction. The plurality ofexecution paths include a predictive path, in which execution proceedsbased on a prediction of a second predictor (prediction).

In one embodiment, the predictor logic or circuitry may be included inbranch circuitry or branch prediction circuitry to facilitate provisionof the prediction functionality.

Further details regarding prediction are provided in U.S. Pat. No.6,513,109, entitled “Method and Apparatus for Implementing ExecutionPredicates in a Computer Processing System,” Gschwind et al., issuedJan. 28, 2003, which is hereby incorporated by reference in itsentirety.

Herein, one or more of the following terms, including memory, mainmemory, storage and main storage, are used interchangeably, unlessotherwise noted explicitly or by context.

As will be appreciated by one skilled in the art, aspects may beembodied as a system, method or computer program product. Accordingly,aspects may take the form of an entirely hardware embodiment, anentirely software embodiment (including firmware, resident software,micro-code, etc.) or an embodiment combining software and hardwareaspects that may all generally be referred to herein as a “circuit,”“module” or “system”. Furthermore, aspects may take the form of acomputer program product embodied in one or more computer readablemedium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may beutilized. The computer readable medium may be a computer readablestorage medium. A computer readable storage medium may be, for example,but not limited to, an electronic, magnetic, optical, electromagnetic,infrared or semiconductor system, apparatus, or device, or any suitablecombination of the foregoing. More specific examples (a non-exhaustivelist) of the computer readable storage medium include the following: anelectrical connection having one or more wires, a portable computerdiskette, a hard disk, a random access memory (RAM), a read-only memory(ROM), an erasable programmable read-only memory (EPROM or Flashmemory), an optical fiber, a portable compact disc read-only memory(CD-ROM), an optical storage device, a magnetic storage device, or anysuitable combination of the foregoing. In the context of this document,a computer readable storage medium may be any tangible medium that cancontain or store a program for use by or in connection with aninstruction execution system, apparatus, or device.

Referring now to FIG. 9, in one example, a computer program product 900includes, for instance, one or more non-transitory computer readablestorage media 902 to store computer readable program code means or logic904 thereon to provide and facilitate one or more aspects of the presentinvention.

Program code embodied on a computer readable medium may be transmittedusing an appropriate medium, including but not limited to, wireless,wireline, optical fiber cable, RF, etc., or any suitable combination ofthe foregoing.

Computer program code for carrying out operations for aspects may bewritten in any combination of one or more programming languages,including an object oriented programming language, such as JAVA,Smalltalk, C++ or the like, and conventional procedural programminglanguages, such as the “C” programming language, assembler or similarprogramming languages. The program code may execute entirely on theuser's computer, partly on the user's computer, as a stand-alonesoftware package, partly on the user's computer and partly on a remotecomputer or entirely on the remote computer or server. In the latterscenario, the remote computer may be connected to the user's computerthrough any type of network, including a local area network (LAN) or awide area network (WAN), or the connection may be made to an externalcomputer (for example, through the Internet using an Internet ServiceProvider).

Aspects are described herein with reference to flowchart illustrationsand/or block diagrams of methods, apparatus (systems) and computerprogram products according to one or more embodiments. It will beunderstood that each block of the flowchart illustrations and/or blockdiagrams, and combinations of blocks in the flowchart illustrationsand/or block diagrams, can be implemented by computer programinstructions. These computer program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks.

These computer program instructions may also be stored in a computerreadable medium that can direct a computer, other programmable dataprocessing apparatus, or other devices to function in a particularmanner, such that the instructions stored in the computer readablemedium produce an article of manufacture including instructions whichimplement the function/act specified in the flowchart and/or blockdiagram block or blocks.

The computer program instructions may also be loaded onto a computer,other programmable data processing apparatus, or other devices to causea series of operational steps to be performed on the computer, otherprogrammable apparatus or other devices to produce a computerimplemented process such that the instructions which execute on thecomputer or other programmable apparatus provide processes forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks.

The flowchart and block diagrams in the figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods and computer program products according to variousembodiments. In this regard, each block in the flowchart or blockdiagrams may represent a module, segment, or portion of code, whichcomprises one or more executable instructions for implementing thespecified logical function(s). It should also be noted that, in somealternative implementations, the functions noted in the block may occurout of the order noted in the figures. For example, two blocks shown insuccession may, in fact, be executed substantially concurrently, or theblocks may sometimes be executed in the reverse order, depending uponthe functionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts, or combinations of special purpose hardware andcomputer instructions.

In addition to the above, one or more aspects may be provided, offered,deployed, managed, serviced, etc. by a service provider who offersmanagement of customer environments. For instance, the service providercan create, maintain, support, etc. computer code and/or a computerinfrastructure that performs one or more aspects for one or morecustomers. In return, the service provider may receive payment from thecustomer under a subscription and/or fee agreement, as examples.Additionally or alternatively, the service provider may receive paymentfrom the sale of advertising content to one or more third parties.

In one aspect, an application may be deployed for performing one or moreaspects. As one example, the deploying of an application comprisesproviding computer infrastructure operable to perform one or moreaspects.

As a further aspect, a computing infrastructure may be deployedcomprising integrating computer readable code into a computing system,in which the code in combination with the computing system is capable ofperforming one or more aspects.

As yet a further aspect, a process for integrating computinginfrastructure comprising integrating computer readable code into acomputer system may be provided. The computer system comprises acomputer readable medium, in which the computer medium comprises one ormore aspects. The code in combination with the computer system iscapable of performing one or more aspects.

Although various embodiments are described above, these are onlyexamples. For example, computing environments of other architectures canincorporate and use one or more aspects. Further, other types ofpredictors may be used and/or other types of instructions may usepredictors without departing from one or more aspects. Further, theremay be more, less and/or different processing stages, and/or there maybe other ways to implement the instructions. Other variations are alsopossible.

Further, other types of computing environments can benefit from one ormore aspects. As an example, a data processing system suitable forstoring and/or executing program code is usable that includes at leasttwo processors coupled directly or indirectly to memory elements througha system bus. The memory elements include, for instance, local memoryemployed during actual execution of the program code, bulk storage, andcache memory which provide temporary storage of at least some programcode in order to reduce the number of times code must be retrieved frombulk storage during execution.

Input/Output or I/O devices (including, but not limited to, keyboards,displays, pointing devices, DASD, tape, CDs, DVDs, thumb drives andother memory media, etc.) can be coupled to the system either directlyor through intervening I/O controllers. Network adapters may also becoupled to the system to enable the data processing system to becomecoupled to other data processing systems or remote printers or storagedevices through intervening private or public networks. Modems, cablemodems, and Ethernet cards are just a few of the available types ofnetwork adapters.

Referring to FIG. 10, representative components of a Host Computersystem 5000 to implement one or more aspects are portrayed. Therepresentative host computer 5000 comprises one or more CPUs 5001 incommunication with computer memory (i.e., central storage) 5002, as wellas I/O interfaces to storage media devices 5011 and networks 5010 forcommunicating with other computers or SANs and the like. The CPU 5001 iscompliant with an architecture having an architected instruction set andarchitected functionality. The CPU 5001 may have dynamic addresstranslation (DAT) 5003 for transforming program addresses (virtualaddresses) into real addresses of memory. A DAT typically includes atranslation lookaside buffer (TLB) 5007 for caching translations so thatlater accesses to the block of computer memory 5002 do not require thedelay of address translation. Typically, a cache 5009 is employedbetween computer memory 5002 and the processor 5001. The cache 5009 maybe hierarchical having a large cache available to more than one CPU andsmaller, faster (lower level) caches between the large cache and eachCPU. In some implementations, the lower level caches are split toprovide separate low level caches for instruction fetching and dataaccesses. In one embodiment, an instruction is fetched from memory 5002by an instruction fetch unit 5004 via a cache 5009. The instruction isdecoded in an instruction decode unit 5006 and dispatched (with otherinstructions in some embodiments) to instruction execution unit or units5008. Typically several execution units 5008 are employed, for examplean arithmetic execution unit, a floating point execution unit and abranch instruction execution unit. The instruction is executed by theexecution unit, accessing operands from instruction specified registersor memory as needed. If an operand is to be accessed (loaded or stored)from memory 5002, a load/store unit 5005 typically handles the accessunder control of the instruction being executed. Instructions may beexecuted in hardware circuits or in internal microcode (firmware) or bya combination of both.

As noted, a computer system includes information in local (or main)storage, as well as addressing, protection, and reference and changerecording. Some aspects of addressing include the format of addresses,the concept of address spaces, the various types of addresses, and themanner in which one type of address is translated to another type ofaddress. Some of main storage includes permanently assigned storagelocations. Main storage provides the system with directly addressablefast-access storage of data. Both data and programs are to be loadedinto main storage (from input devices) before they can be processed.

Main storage may include one or more smaller, faster-access bufferstorages, sometimes called caches. A cache is typically physicallyassociated with a CPU or an I/O processor. The effects, except onperformance, of the physical construction and use of distinct storagemedia are generally not observable by the program.

Separate caches may be maintained for instructions and for dataoperands. Information within a cache is maintained in contiguous byteson an integral boundary called a cache block or cache line (or line, forshort). A model may provide an EXTRACT CACHE ATTRIBUTE instruction whichreturns the size of a cache line in bytes. A model may also providePREFETCH DATA and PREFETCH DATA RELATIVE LONG instructions which effectsthe prefetching of storage into the data or instruction cache or thereleasing of data from the cache.

Storage is viewed as a long horizontal string of bits. For mostoperations, accesses to storage proceed in a left-to-right sequence. Thestring of bits is subdivided into units of eight bits. An eight-bit unitis called a byte, which is the basic building block of all informationformats. Each byte location in storage is identified by a uniquenonnegative integer, which is the address of that byte location or,simply, the byte address. Adjacent byte locations have consecutiveaddresses, starting with 0 on the left and proceeding in a left-to-rightsequence. Addresses are unsigned binary integers and are 24, 31, or 64bits.

Information is transmitted between storage and a CPU or a channelsubsystem one byte, or a group of bytes, at a time. Unless otherwisespecified, in, for instance, the z/Architecture, a group of bytes instorage is addressed by the leftmost byte of the group. The number ofbytes in the group is either implied or explicitly specified by theoperation to be performed. When used in a CPU operation, a group ofbytes is called a field. Within each group of bytes, in, for instance,the z/Architecture, bits are numbered in a left-to-right sequence. Inthe z/Architecture, the leftmost bits are sometimes referred to as the“high-order” bits and the rightmost bits as the “low-order” bits. Bitnumbers are not storage addresses, however. Only bytes can be addressed.To operate on individual bits of a byte in storage, the entire byte isaccessed. The bits in a byte are numbered 0 through 7, from left toright (in, e.g., the z/Architecture). The bits in an address may benumbered 8-31 or 40-63 for 24-bit addresses, or 1-31 or 33-63 for 31-bitaddresses; they are numbered 0-63 for 64-bit addresses. Within any otherfixed-length format of multiple bytes, the bits making up the format areconsecutively numbered starting from 0. For purposes of error detection,and in preferably for correction, one or more check bits may betransmitted with each byte or with a group of bytes. Such check bits aregenerated automatically by the machine and cannot be directly controlledby the program. Storage capacities are expressed in number of bytes.When the length of a storage-operand field is implied by the operationcode of an instruction, the field is said to have a fixed length, whichcan be one, two, four, eight, or sixteen bytes. Larger fields may beimplied for some instructions. When the length of a storage-operandfield is not implied but is stated explicitly, the field is said to havea variable length. Variable-length operands can vary in length byincrements of one byte (or with some instructions, in multiples of twobytes or other multiples). When information is placed in storage, thecontents of only those byte locations are replaced that are included inthe designated field, even though the width of the physical path tostorage may be greater than the length of the field being stored.

Certain units of information are to be on an integral boundary instorage. A boundary is called integral for a unit of information whenits storage address is a multiple of the length of the unit in bytes.Special names are given to fields of 2, 4, 8, and 16 bytes on anintegral boundary. A halfword is a group of two consecutive bytes on atwo-byte boundary and is the basic building block of instructions. Aword is a group of four consecutive bytes on a four-byte boundary. Adoubleword is a group of eight consecutive bytes on an eight-byteboundary. A quadword is a group of 16 consecutive bytes on a 16-byteboundary. When storage addresses designate halfwords, words,doublewords, and quadwords, the binary representation of the addresscontains one, two, three, or four rightmost zero bits, respectively.Instructions are to be on two-byte integral boundaries. The storageoperands of most instructions do not have boundary-alignmentrequirements.

On devices that implement separate caches for instructions and dataoperands, a significant delay may be experienced if the program storesinto a cache line from which instructions are subsequently fetched,regardless of whether the store alters the instructions that aresubsequently fetched.

In one embodiment, the invention may be practiced by software (sometimesreferred to licensed internal code, firmware, micro-code, milli-code,pico-code and the like, any of which would be consistent with one ormore aspects). Referring to FIG. 10, software program code whichembodies one or more aspects may be accessed by processor 5001 of thehost system 5000 from long-term storage media devices 5011, such as aCD-ROM drive, tape drive or hard drive. The software program code may beembodied on any of a variety of known media for use with a dataprocessing system, such as a diskette, hard drive, or CD-ROM. The codemay be distributed on such media, or may be distributed to users fromcomputer memory 5002 or storage of one computer system over a network5010 to other computer systems for use by users of such other systems.

The software program code includes an operating system which controlsthe function and interaction of the various computer components and oneor more application programs. Program code is normally paged fromstorage media device 5011 to the relatively higher-speed computerstorage 5002 where it is available for processing by processor 5001. Thetechniques and methods for embodying software program code in memory, onphysical media, and/or distributing software code via networks are wellknown and will not be further discussed herein. Program code, whencreated and stored on a tangible medium (including but not limited toelectronic memory modules (RAM), flash memory, Compact Discs (CDs),DVDs, Magnetic Tape and the like is often referred to as a “computerprogram product”. The computer program product medium is typicallyreadable by a processing circuit preferably in a computer system forexecution by the processing circuit.

FIG. 11 illustrates a representative workstation or server hardwaresystem in which one or more aspects may be practiced. The system 5020 ofFIG. 11 comprises a representative base computer system 5021, such as apersonal computer, a workstation or a server, including optionalperipheral devices. The base computer system 5021 includes one or moreprocessors 5026 and a bus employed to connect and enable communicationbetween the processor(s) 5026 and the other components of the system5021 in accordance with known techniques. The bus connects the processor5026 to memory 5025 and long-term storage 5027 which can include a harddrive (including any of magnetic media, CD, DVD and Flash Memory forexample) or a tape drive for example. The system 5021 might also includea user interface adapter, which connects the microprocessor 5026 via thebus to one or more interface devices, such as a keyboard 5024, a mouse5023, a printer/scanner 5030 and/or other interface devices, which canbe any user interface device, such as a touch sensitive screen,digitized entry pad, etc. The bus also connects a display device 5022,such as an LCD screen or monitor, to the microprocessor 5026 via adisplay adapter.

The system 5021 may communicate with other computers or networks ofcomputers by way of a network adapter capable of communicating 5028 witha network 5029. Example network adapters are communications channels,token ring, Ethernet or modems. Alternatively, the system 5021 maycommunicate using a wireless interface, such as a CDPD (cellular digitalpacket data) card. The system 5021 may be associated with such othercomputers in a Local Area Network (LAN) or a Wide Area Network (WAN), orthe system 5021 can be a client in a client/server arrangement withanother computer, etc. All of these configurations, as well as theappropriate communications hardware and software, are known in the art.

FIG. 12 illustrates a data processing network 5040 in which one or moreaspects may be practiced. The data processing network 5040 may include aplurality of individual networks, such as a wireless network and a wirednetwork, each of which may include a plurality of individualworkstations 5041, 5042, 5043, 5044. Additionally, as those skilled inthe art will appreciate, one or more LANs may be included, where a LANmay comprise a plurality of intelligent workstations coupled to a hostprocessor.

Still referring to FIG. 12, the networks may also include mainframecomputers or servers, such as a gateway computer (client server 5046) orapplication server (remote server 5048 which may access a datarepository and may also be accessed directly from a workstation 5045). Agateway computer 5046 serves as a point of entry into each individualnetwork. A gateway is needed when connecting one networking protocol toanother. The gateway 5046 may be preferably coupled to another network(the Internet 5047 for example) by means of a communications link. Thegateway 5046 may also be directly coupled to one or more workstations5041, 5042, 5043, 5044 using a communications link. The gateway computermay be implemented utilizing an IBM eServer™ System z server availablefrom International Business Machines Corporation.

Referring concurrently to FIG. 11 and FIG. 12, software programming codewhich may embody one or more aspects of the present invention may beaccessed by the processor 5026 of the system 5020 from long-term storagemedia 5027, such as a CD-ROM drive or hard drive. The softwareprogramming code may be embodied on any of a variety of known media foruse with a data processing system, such as a diskette, hard drive, orCD-ROM. The code may be distributed on such media, or may be distributedto users 5050, 5051 from the memory or storage of one computer systemover a network to other computer systems for use by users of such othersystems.

Alternatively, the programming code may be embodied in the memory 5025,and accessed by the processor 5026 using the processor bus. Suchprogramming code includes an operating system which controls thefunction and interaction of the various computer components and one ormore application programs 5032. Program code is normally paged fromstorage media 5027 to high-speed memory 5025 where it is available forprocessing by the processor 5026. The techniques and methods forembodying software programming code in memory, on physical media, and/ordistributing software code via networks are well known and will not befurther discussed herein. Program code, when created and stored on atangible medium (including but not limited to electronic memory modules(RAM), flash memory, Compact Discs (CDs), DVDs, Magnetic Tape and thelike is often referred to as a “computer program product”. The computerprogram product medium is typically readable by a processing circuitpreferably in a computer system for execution by the processing circuit.

The cache that is most readily available to the processor (normallyfaster and smaller than other caches of the processor) is the lowest (L1or level one) cache and main store (main memory) is the highest levelcache (L3 if there are 3 levels). The lowest level cache is oftendivided into an instruction cache (I-Cache) holding machine instructionsto be executed and a data cache (D-Cache) holding data operands.

Referring to FIG. 13, an exemplary processor embodiment is depicted forprocessor 5026. Typically one or more levels of cache 5053 are employedto buffer memory blocks in order to improve processor performance. Thecache 5053 is a high speed buffer holding cache lines of memory datathat are likely to be used. Typical cache lines are 64, 128 or 256 bytesof memory data. Separate caches are often employed for cachinginstructions than for caching data. Cache coherence (synchronization ofcopies of lines in memory and the caches) is often provided by various“snoop” algorithms well known in the art. Main memory storage 5025 of aprocessor system is often referred to as a cache. In a processor systemhaving 4 levels of cache 5053, main storage 5025 is sometimes referredto as the level 5 (L5) cache since it is typically faster and only holdsa portion of the non-volatile storage (DASD, tape etc) that is availableto a computer system. Main storage 5025 “caches” pages of data paged inand out of the main storage 5025 by the operating system.

A program counter (instruction counter) 5061 keeps track of the addressof the current instruction to be executed. A program counter in az/Architecture processor is 64 bits and can be truncated to 31 or 24bits to support prior addressing limits. A program counter is typicallyembodied in a PSW (program status word) of a computer such that itpersists during context switching. Thus, a program in progress, having aprogram counter value, may be interrupted by, for example, the operatingsystem (context switch from the program environment to the operatingsystem environment). The PSW of the program maintains the programcounter value while the program is not active, and the program counter(in the PSW) of the operating system is used while the operating systemis executing. Typically, the program counter is incremented by an amountequal to the number of bytes of the current instruction. RISC (ReducedInstruction Set Computing) instructions are typically fixed length whileCISC (Complex Instruction Set Computing) instructions are typicallyvariable length. Instructions of the IBM z/Architecture are CISCinstructions having a length of 2, 4 or 6 bytes. The Program counter5061 is modified by either a context switch operation or a branch takenoperation of a branch instruction for example. In a context switchoperation, the current program counter value is saved in the programstatus word along with other state information about the program beingexecuted (such as condition codes), and a new program counter value isloaded pointing to an instruction of a new program module to beexecuted. A branch taken operation is performed in order to permit theprogram to make decisions or loop within the program by loading theresult of the branch instruction into the program counter 5061.

Typically an instruction fetch unit 5055 is employed to fetchinstructions on behalf of the processor 5026. The fetch unit eitherfetches “next sequential instructions”, target instructions of branchtaken instructions, or first instructions of a program following acontext switch. Modern Instruction fetch units often employ prefetchtechniques to speculatively prefetch instructions based on thelikelihood that the prefetched instructions might be used. For example,a fetch unit may fetch 16 bytes of instruction that includes the nextsequential instruction and additional bytes of further sequentialinstructions.

The fetched instructions are then executed by the processor 5026. In anembodiment, the fetched instruction(s) are passed to a dispatch unit5056 of the fetch unit. The dispatch unit decodes the instruction(s) andforwards information about the decoded instruction(s) to appropriateunits 5057, 5058, 5060. An execution unit 5057 will typically receiveinformation about decoded arithmetic instructions from the instructionfetch unit 5055 and will perform arithmetic operations on operandsaccording to the opcode of the instruction. Operands are provided to theexecution unit 5057 preferably either from memory 5025, architectedregisters 5059 or from an immediate field of the instruction beingexecuted. Results of the execution, when stored, are stored either inmemory 5025, registers 5059 or in other machine hardware (such ascontrol registers, PSW registers and the like).

A processor 5026 typically has one or more units 5057, 5058, 5060 forexecuting the function of the instruction. Referring to FIG. 14A, anexecution unit 5057 may communicate with architected general registers5059, a decode/dispatch unit 5056, a load store unit 5060, and other5065 processor units by way of interfacing logic 5071. An execution unit5057 may employ several register circuits 5067, 5068, 5069 to holdinformation that the arithmetic logic unit (ALU) 5066 will operate on.The ALU performs arithmetic operations such as add, subtract, multiplyand divide as well as logical function such as and, or and exclusive-or(XOR), rotate and shift. Preferably the ALU supports specializedoperations that are design dependent. Other circuits may provide otherarchitected facilities 5072 including condition codes and recoverysupport logic for example. Typically the result of an ALU operation isheld in an output register circuit 5070 which can forward the result toa variety of other processing functions. There are many arrangements ofprocessor units, the present description is only intended to provide arepresentative understanding of one embodiment.

An ADD instruction for example would be executed in an execution unit5057 having arithmetic and logical functionality while a floating pointinstruction for example would be executed in a floating point executionhaving specialized floating point capability. Preferably, an executionunit operates on operands identified by an instruction by performing anopcode defined function on the operands. For example, an ADD instructionmay be executed by an execution unit 5057 on operands found in tworegisters 5059 identified by register fields of the instruction.

The execution unit 5057 performs the arithmetic addition on two operandsand stores the result in a third operand where the third operand may bea third register or one of the two source registers. The execution unitpreferably utilizes an Arithmetic Logic Unit (ALU) 5066 that is capableof performing a variety of logical functions such as Shift, Rotate, And,Or and XOR as well as a variety of algebraic functions including any ofadd, subtract, multiply, divide. Some ALUs 5066 are designed for scalaroperations and some for floating point. Data may be Big Endian (wherethe least significant byte is at the highest byte address) or LittleEndian (where the least significant byte is at the lowest byte address)depending on architecture. The IBM z/Architecture is Big Endian. Signedfields may be sign and magnitude, 1's complement or 2's complementdepending on architecture. A 2's complement number is advantageous inthat the ALU does not need to design a subtract capability since eithera negative value or a positive value in 2's complement requires only anaddition within the ALU. Numbers are commonly described in shorthand,where a 12 bit field defines an address of a 4,096 byte block and iscommonly described as a 4 Kbyte (Kilo-byte) block, for example.

Referring to FIG. 14B, branch instruction information for executing abranch instruction is typically sent to a branch unit 5058 which oftenemploys a branch prediction algorithm such as a branch history table5082 to predict the outcome of the branch before other conditionaloperations are complete. The target of the current branch instructionwill be fetched and speculatively executed before the conditionaloperations are complete. When the conditional operations are completedthe speculatively executed branch instructions are either completed ordiscarded based on the conditions of the conditional operation and thespeculated outcome. A typical branch instruction may test conditioncodes and branch to a target address if the condition codes meet thebranch requirement of the branch instruction, a target address may becalculated based on several numbers including ones found in registerfields or an immediate field of the instruction for example. The branchunit 5058 may employ an ALU 5074 having a plurality of input registercircuits 5075, 5076, 5077 and an output register circuit 5080. Thebranch unit 5058 may communicate with general registers 5059, decodedispatch unit 5056 or other circuits 5073, for example.

The execution of a group of instructions can be interrupted for avariety of reasons including a context switch initiated by an operatingsystem, a program exception or error causing a context switch, an I/Ointerruption signal causing a context switch or multi-threading activityof a plurality of programs (in a multi-threaded environment), forexample. Preferably a context switch action saves state informationabout a currently executing program and then loads state informationabout another program being invoked. State information may be saved inhardware registers or in memory for example. State informationpreferably comprises a program counter value pointing to a nextinstruction to be executed, condition codes, memory translationinformation and architected register content. A context switch activitycan be exercised by hardware circuits, application programs, operatingsystem programs or firmware code (microcode, pico-code or licensedinternal code (LIC)) alone or in combination.

A processor accesses operands according to instruction defined methods.The instruction may provide an immediate operand using the value of aportion of the instruction, may provide one or more register fieldsexplicitly pointing to either general purpose registers or specialpurpose registers (floating point registers for example). Theinstruction may utilize implied registers identified by an opcode fieldas operands. The instruction may utilize memory locations for operands.A memory location of an operand may be provided by a register, animmediate field, or a combination of registers and immediate field asexemplified by the z/Architecture long displacement facility wherein theinstruction defines a base register, an index register and an immediatefield (displacement field) that are added together to provide theaddress of the operand in memory for example. Location herein typicallyimplies a location in main memory (main storage) unless otherwiseindicated.

Referring to FIG. 14C, a processor accesses storage using a load/storeunit 5060. The load/store unit 5060 may perform a load operation byobtaining the address of the target operand in memory 5053 and loadingthe operand in a register 5059 or another memory 5053 location, or mayperform a store operation by obtaining the address of the target operandin memory 5053 and storing data obtained from a register 5059 or anothermemory 5053 location in the target operand location in memory 5053. Theload/store unit 5060 may be speculative and may access memory in asequence that is out-of-order relative to instruction sequence, howeverthe load/store unit 5060 is to maintain the appearance to programs thatinstructions were executed in order. A load/store unit 5060 maycommunicate with general registers 5059, decode/dispatch unit 5056,cache/memory interface 5053 or other elements 5083 and comprises variousregister circuits, ALUs 5085 and control logic 5090 to calculate storageaddresses and to provide pipeline sequencing to keep operationsin-order. Some operations may be out of order but the load/store unitprovides functionality to make the out of order operations to appear tothe program as having been performed in order, as is well known in theart.

Preferably addresses that an application program “sees” are oftenreferred to as virtual addresses. Virtual addresses are sometimesreferred to as “logical addresses” and “effective addresses”. Thesevirtual addresses are virtual in that they are redirected to physicalmemory location by one of a variety of dynamic address translation (DAT)technologies including, but not limited to, simply prefixing a virtualaddress with an offset value, translating the virtual address via one ormore translation tables, the translation tables preferably comprising atleast a segment table and a page table alone or in combination,preferably, the segment table having an entry pointing to the pagetable. In the z/Architecture, a hierarchy of translation is providedincluding a region first table, a region second table, a region thirdtable, a segment table and an optional page table. The performance ofthe address translation is often improved by utilizing a translationlookaside buffer (TLB) which comprises entries mapping a virtual addressto an associated physical memory location. The entries are created whenthe DAT translates a virtual address using the translation tables.Subsequent use of the virtual address can then utilize the entry of thefast TLB rather than the slow sequential translation table accesses. TLBcontent may be managed by a variety of replacement algorithms includingLRU (Least Recently used).

In the case where the processor is a processor of a multi-processorsystem, each processor has responsibility to keep shared resources, suchas I/O, caches, TLBs and memory, interlocked for coherency. Typically,“snoop” technologies will be utilized in maintaining cache coherency. Ina snoop environment, each cache line may be marked as being in any oneof a shared state, an exclusive state, a changed state, an invalid stateand the like in order to facilitate sharing.

I/O units 5054 (FIG. 13) provide the processor with means for attachingto peripheral devices including tape, disc, printers, displays, andnetworks for example. I/O units are often presented to the computerprogram by software drivers. In mainframes, such as the System z fromIBM®, channel adapters and open system adapters are I/O units of themainframe that provide the communications between the operating systemand peripheral devices.

Further, other types of computing environments can benefit from one ormore aspects. As an example, an environment may include an emulator(e.g., software or other emulation mechanisms), in which a particulararchitecture (including, for instance, instruction execution,architected functions, such as address translation, and architectedregisters) or a subset thereof is emulated (e.g., on a native computersystem having a processor and memory). In such an environment, one ormore emulation functions of the emulator can implement one or moreaspects of the present invention, even though a computer executing theemulator may have a different architecture than the capabilities beingemulated. As one example, in emulation mode, the specific instruction oroperation being emulated is decoded, and an appropriate emulationfunction is built to implement the individual instruction or operation.

In an emulation environment, a host computer includes, for instance, amemory to store instructions and data; an instruction fetch unit tofetch instructions from memory and to optionally, provide localbuffering for the fetched instruction; an instruction decode unit toreceive the fetched instructions and to determine the type ofinstructions that have been fetched; and an instruction execution unitto execute the instructions. Execution may include loading data into aregister from memory; storing data back to memory from a register; orperforming some type of arithmetic or logical operation, as determinedby the decode unit. In one example, each unit is implemented insoftware. For instance, the operations being performed by the units areimplemented as one or more subroutines within emulator software.

More particularly, in a mainframe, architected machine instructions areused by programmers, usually today “C” programmers, often by way of acompiler application. These instructions stored in the storage mediummay be executed natively in a z/Architecture IBM® Server, oralternatively in machines executing other architectures. They can beemulated in the existing and in future IBM® mainframe servers and onother machines of IBM® (e.g., Power Systems servers and System x®Servers). They can be executed in machines running Linux on a widevariety of machines using hardware manufactured by IBM®, Intel®, AMD™,and others. Besides execution on that hardware under a z/Architecture,Linux can be used as well as machines which use emulation by Hercules,UMX, or FSI (Fundamental Software, Inc), where generally execution is inan emulation mode. In emulation mode, emulation software is executed bya native processor to emulate the architecture of an emulated processor.

The native processor typically executes emulation software comprisingeither firmware or a native operating system to perform emulation of theemulated processor. The emulation software is responsible for fetchingand executing instructions of the emulated processor architecture. Theemulation software maintains an emulated program counter to keep trackof instruction boundaries. The emulation software may fetch one or moreemulated machine instructions at a time and convert the one or moreemulated machine instructions to a corresponding group of native machineinstructions for execution by the native processor. These convertedinstructions may be cached such that a faster conversion can beaccomplished. Notwithstanding, the emulation software is to maintain thearchitecture rules of the emulated processor architecture so as toassure operating systems and applications written for the emulatedprocessor operate correctly. Furthermore, the emulation software is toprovide resources identified by the emulated processor architectureincluding, but not limited to, control registers, general purposeregisters, floating point registers, dynamic address translationfunction including segment tables and page tables for example, interruptmechanisms, context switch mechanisms, Time of Day (TOD) clocks andarchitected interfaces to I/O subsystems such that an operating systemor an application program designed to run on the emulated processor, canbe run on the native processor having the emulation software.

A specific instruction being emulated is decoded, and a subroutine iscalled to perform the function of the individual instruction. Anemulation software function emulating a function of an emulatedprocessor is implemented, for example, in a “C” subroutine or driver, orsome other method of providing a driver for the specific hardware aswill be within the skill of those in the art after understanding thedescription of one or more embodiments. Various software and hardwareemulation patents including, but not limited to U.S. Pat. No. 5,551,013,entitled “Multiprocessor for Hardware Emulation”, by Beausoleil et al.;and U.S. Pat. No. 6,009,261, entitled “Preprocessing of Stored TargetRoutines for Emulating Incompatible Instructions on a Target Processor”,by Scalzi et al; and U.S. Pat. No. 5,574,873, entitled “Decoding GuestInstruction to Directly Access Emulation Routines that Emulate the GuestInstructions”, by Davidian et al; and U.S. Pat. No. 6,308,255, entitled“Symmetrical Multiprocessing Bus and Chipset Used for CoprocessorSupport Allowing Non-Native Code to Run in a System”, by Gorishek et al;and U.S. Pat. No. 6,463,582, entitled “Dynamic Optimizing Object CodeTranslator for Architecture Emulation and Dynamic Optimizing Object CodeTranslation Method”, by Lethin et al; and U.S. Pat. No. 5,790,825,entitled “Method for Emulating Guest Instructions on a Host ComputerThrough Dynamic Recompilation of Host Instructions”, by Eric Traut, eachof which is hereby incorporated herein by reference in its entirety; andmany others, illustrate a variety of known ways to achieve emulation ofan instruction format architected for a different machine for a targetmachine available to those skilled in the art.

In FIG. 15, an example of an emulated host computer system 5092 isprovided that emulates a host computer system 5000′ of a hostarchitecture. In the emulated host computer system 5092, the hostprocessor (CPU) 5091 is an emulated host processor (or virtual hostprocessor) and comprises an emulation processor 5093 having a differentnative instruction set architecture than that of the processor 5091 ofthe host computer 5000′. The emulated host computer system 5092 hasmemory 5094 accessible to the emulation processor 5093. In the exampleembodiment, the memory 5094 is partitioned into a host computer memory5096 portion and an emulation routines 5097 portion. The host computermemory 5096 is available to programs of the emulated host computer 5092according to host computer architecture. The emulation processor 5093executes native instructions of an architected instruction set of anarchitecture other than that of the emulated processor 5091, the nativeinstructions obtained from emulation routines memory 5097, and mayaccess a host instruction for execution from a program in host computermemory 5096 by employing one or more instruction(s) obtained in asequence & access/decode routine which may decode the hostinstruction(s) accessed to determine a native instruction executionroutine for emulating the function of the host instruction accessed.Other facilities that are defined for the host computer system 5000′architecture may be emulated by architected facilities routines,including such facilities as general purpose registers, controlregisters, dynamic address translation and I/O subsystem support andprocessor cache, for example. The emulation routines may also takeadvantage of functions available in the emulation processor 5093 (suchas general registers and dynamic translation of virtual addresses) toimprove performance of the emulation routines. Special hardware andoff-load engines may also be provided to assist the processor 5093 inemulating the function of the host computer 5000′.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising”, when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below, if any, areintended to include any structure, material, or act for performing thefunction in combination with other claimed elements as specificallyclaimed. The description of one or more aspects has been presented forpurposes of illustration and description, but is not intended to beexhaustive or limited to the invention in the form disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of one or moreaspects. The embodiment was chosen and described in order to bestexplain the principles of the one or more aspects and the practicalapplication, and to enable others of ordinary skill in the art tounderstand the one or more aspects for various embodiments with variousmodifications as are suited to the particular use contemplated.

What is claimed is:
 1. A method of facilitating execution of aninstruction in a computing environment, said method comprising: checkinga confidence level associated with the instruction; based on theconfidence level being a first value, unconditionally performing apredicted operation of the instruction, the predicted operation based ona predictor associated with the instruction; and based on the confidencelevel being a second value, conditionally performing a specifiedoperation of the instruction, the specified operation based on adetermined condition.
 2. The method of claim 1, wherein the confidencelevel is one of: a part of the predictor; or another predictor separatefrom the predictor.
 3. The method of claim 1, wherein the predictedoperation comprises one of a load operation, suppression of a loadoperation, or selection of one datum of a plurality of data, and whereinthe specified operation comprises one of a load operation, suppressionof a load operation, or selection of one datum of a plurality of data.4. The method of claim 1, wherein the instruction is a load on conditioninstruction, the determined condition is an input to the instruction,and one or more of the predicted operation and the specified operationis a load operation or a suppression of a load operation.
 5. The methodof claim 1, wherein the instruction is a data selection instruction, thedetermined condition is an input to the instruction, and one or more ofthe predicted operation and the specified operation is a selection of afirst datum or a selection of a second datum.
 6. The method of claim 1,further comprising: based on unconditionally performing the predictedoperation, checking an accuracy of predicating the predicted operation;and continuing processing associated with the instruction based on thechecking.
 7. The method of claim 6, wherein the continuing processingcomprises one of: completing the instruction based on the checkingindicating an accurate prediction; and performing recovery based on thechecking indicating an inaccurate prediction.
 8. The method of claim 1,further comprising updating a prediction data structure, the predictiondata structure to include one or more of the confidence level and thepredictor.
 9. The method of claim 1, wherein based on the confidencelevel being the second value, obtaining the determined condition,wherein the obtaining comprises obtaining the determined condition fromone of a condition code or a register.
 10. The method of claim 1,wherein the unconditionally performing the predicted operationcomprises: generating an implementation to unconditionally perform thepredicted operation; and executing the implementation to unconditionallyperform the predicted operation.